Hardware system development often involves debugging complex designs. As such, various circuits and protocols have been created to make the debugging process more efficient. For example, the Joint Test Action Group (“JTAG”) standard was developed specifically for this purpose. The standard comprises a JTAG cable connecting a user's host computer to an integrated circuit. The cable includes circuitry to facilitate a variety of debugging operations, such as the ones described below.
The operations typically used when debugging a processor over JTAG include entry into debug mode, reading and writing of memory elements on the integrated circuit, and exit from debug mode. These functions permit users to diagnose a system by observing and changing the state of that system after it encounters a problem. The debug instructions are carried out on the same instruction pipeline that is used during normal operation.
A problem can arise when the target chip includes a processor whose data bus has hung. For instance, the processor may initiate a read instruction that fails to complete, thereby suspending operation on the data bus indefinitely. The instruction pipeline is unable to finish the read instruction, and thus cannot perform debugging instructions (e.g., entry into debug mode). Under these circumstances, the only option is to reset the processor, which results in loss of information about the system's state at the time of the hang.
In view of the foregoing, it would be desirable to develop circuitry and methods to force the processor out of a hung state, thereby permitting entry into debug mode. Furthermore, it would be desirable to perform this task in a manner that preserves as much system state as possible, for future reading and manipulation during debug mode.